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v3.2.8
FPGA developement merged to WP 04.
FPGA Developer forum recently launched - scope is to standarize FPGA - Angel is a leader, DMCS can be observer,
ICS Project level update:
- MTCA crates standarization
Susanne Regnell - ask about EPICS training - new dates to be announced
Commissioning activites needs to be included in the time plan and cost!!!
Fabio presentation:
Is DMCS using example 0? As a reference, but no files from example 0 are added to the project.
Request to config flag to enable ILA.
State of simulations: the simulation of the entire project is probably not working, the unit tests probably are.
Command line tools are working on both Concurrent and QorIQ CPUs.
Pico calibration values readout possible only on QorIQ CPU.
- "software done in accordance to the guidelines...." - now We know it is E3,
- KV - is it ok to have single IOC for single crate...
- scalability discussion:
- discussion summary from previous meetings:
- use library, not dev. IPMI from scratch,
- even if EPICS IOC is not availale still provide chassis monitoring - on the lib level, use info fetched by deamon,
- HL: why to use "openipmi (if needed)"? PP: In order to cover specific IPMI requests not covered by openHPI (openHPI.org)
- KV: is it posible to rewrite openhpid deamon to have it as a part of EPICS?
PP: Yes, it is open solution, it requires some effort. Needs to be decided. This can be done with more work to DMCS but if so - one will loose portability and community support.
PP: Thank You
1. Presentation on Indico
- 50 boards are xpected to go into production in 1 month
- firmware is using framwork from Christian
- BSP provided by NCBJ
- on top of this two dedicated RTM support pkgs are made
- layout of fw is presented
- some changes to BSP done at DMCS
- DDR controller not working, must be corrected at NCBJ
- vivado version required by BSP cannot be used with ESS Framework (2018.2)
- NCBJ is local IOxOS
- we are not using MGT links, which require higher version of Vivado
- plans for future
- some problems with most recent version form ESS Framework
- NCBJ must correct BSP
- PCIe vendor ID should be requestedby ESS
- software is presented
- 3 layers of SW, still no epics ready
- driver based on Xilinx core - 2 simple changes made to the code
- library provides API
- some examples provided for API
- function of bench signal generator
Discussion:
- some questions to Christian
- what is trigger scheme ?
- should the delay be generated internally or will it come from timing system ?
- discussion on timing will follow
- common component for trigger delay as part of framework ?
- idea will come form ESS
- piezo needs trigger before the pulse
- number of EVRS and trigger lines in the system is not enough
- packaging
- should we provide RPM or E3 ? - provide makefile and packaging will be done by ESS (cmake, make, autotools)